The invention relates to a multiple voltage environment input pad with hysteresis.
The invention also relates to a multiple voltage environment input pad with a circuit input.
In multiple voltage environments the external voltage may differ from the core voltage. The necessary interfacing of an external signal is carried out by a level shifter circuit and a buffer circuit mainly responsible for signal recognition and noise reduction. Together they form the so-called input pad. External signal noise is suppressed by applying hysteresis techniques in which two voltage thresholds (trigger points) are being used. By exceeding the highest of the two the output signal of the interface circuitry becomes 1 and by dropping below the lowest of the two the output signal becomes xe2x80x9c0xe2x80x9d. At in between voltages, the noise immunity region, the output signal remains unchanged.
It is an object of the invention to increase the noise immunity region of the input pad. It is another object of the invention to improve output characteristics of the input pad.
A multiple voltage environment input pad with hysteresis according to the invention thereto is characterized by a level shifter circuit and a buffer circuit, which level shifter circuit comprises a series pass transistor and which buffer circuit defines upper and lower trigger points voltages of the input pad and by a transistorized capacitor connected in parallel to the series pass transistor.
A multiple voltage environment input pad with a circuit input thereto is characterized by a level shifter circuit and buffer circuit, which level shifter circuit comprises a level shifter circuit input connected to the circuit input and a level shifter circuit output, which buffer circuit comprises an inverter comprising at least two transistors of opposite polarities, with an input, connected to the level shifter circuit output, and an output, twin controllable voltage dividers of opposite types, each with two controllable voltage divider inputs and a controllable voltage divider output, wherein for each of the controllable voltage dividers one of the inputs is connected to the level shifter circuit output and the other one of the inputs is connected to the inverter output, and wherein for each of the controllable voltage dividers the voltage divider output is connected to a current input connection of a transistor of corresponding type of the inverter, an input pad output being connected to the inverter output.
The input pad is used to interface a signal from the bond pad to the core circuit. In a multiple voltage environment the external voltage on the bond pad and the voltage supplied to the core circuit may be different. The external voltage is normally higher than the internal core voltage. Therefore it is necessary to convert an external signal level to a correct voltage level before passing it to the core circuit. Such transformation of voltage level is done by the level shifter circuit.
The external signal coming to the bond pad is not a very clean signal. It may contain some noise pulses and ringing. To avoid a noisy signal to pass to the core and to achieve a clean signal the input pad is specified with an upper trigger point and a lower trigger point specification. The upper trigger point is the input voltage level at which an output voltage of the input pad goes high, the lower trigger point is the input voltage level at which the output of the input pad goes low. If the output of the input pad is already high the output remains unchanged as long as the input signal does not pass the lower trigger point in a downward direction. If the output of the input pad is already low the output remains unchanged as long as the input signal does not pass the upper trigger point in an upward direction. The region between the upper and lower trigger points defines the noise immunity of the circuit. If the upper and lower trigger points are very close to each other then a noise pulse or a ringing of the input signal close to the trigger points will cause the output to change. In a noisy environment it is required that the hysteresis has a high value and the input pad should have upper and lower trigger points that are as far away from each other as possible within boundaries set by the specifications of the circuit to which the output signal of the input pad is to be delivered.
Functionality of an input pad with hysteresis used in a multiple voltage environment can be divided into two parts. The first part consists of interfacing an external voltage level to the core voltage levels. The second part consists of proper recognition of an input signal as xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d when the input signal crosses the upper trigger point and the lower trigger point, respectively. This requirement holds in particular when the input signal is noisy and does not have a clear xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d condition.
The first part of the functionality is achieved by a level shifter circuit which comprises a series pass transistor. The second part of the functionality is achieved by a buffer circuit whose upper and lower trigger points are controlled by controllable potential dividers controlling source voltages of transistors of an inverter.
A preferred embodiment of an input pad according to the invention is characterized in that the level shifter circuit comprises a series pass transistor and in that a transistorized capacitor is connected in parallel to the series pass transistor.
A transistorized capacitor is formed by connecting the drain, the source and the bulk together of a transistor to form one terminal while the gate of the transistor forms the other terminal. Thereby it is achieved that an input signal at the input of the level shifter circuit is coupled to the output of the level shifter circuit (charge coupling). Thereby a pulse voltage at the input of the level shifter circuit is distributed between the transistorized capacitor and an input capacitance of the buffer circuit. The transistorized capacitor plays a dual role of speeding up the input pad and also enhancing the voltage at the output of the level shifter circuit when a high voltage appears at the input of the level shifter circuit. Thereby it is possible to achieve high values of allowable input signals, in particular input signals having a higher value than a supply voltage to the input pad. It is to be noted that there is no charge accumulation across the transistorized capacitor as it is shunted by a very low resistance of the series pass transistor, which is permanently on.
A further embodiment of an input pad according to the invention is characterized in that a transistorized capacitor is connected between the output of the inverter and the output of one of the two controllable voltage dividers.
Thereby a positive feedback is introduced, whereby the input pad is able to accept higher values of an input signal at higher frequencies.
A further embodiment of an input pad according to the invention is characterized in that a weak pull up element comprises a pull up transistor connected between a supply voltage and the output of the level shifter circuit and in that a control input of the pull up transistor is connected to the output of the first inverter.
Thereby it is achieved that a weak pull up occurs at the output of the level shifter circuit when an input signal goes high and crosses the upper trigger point.